d trigger verilog description
The flip-flop is a memory storage device with two stable states. It is the most basic logic unit that constitutes a variety of sequential circuits, and is also an important unit circuit in digital logic circuits.
It has a wide range of applications in digital systems and computers. The flip-flop has two stable states, namely "0" and "1", which can be flipped from one stable state to another under the action of a certain external signal.
The flip-flop has a trigger composed of an integrated flip-flop and a gate. There are two types of trigger modes: level trigger and edge trigger.
The D flip-flop flips at the leading edge of the clock pulse CP (positive transition 0→1), and the state of the flip-flop depends on the state of the D-end before the rising edge of the pulse of the CP, that is, the second state = D. Therefore, it has two functions of setting 0 and setting 1. Due to
The circuit has a blocking function during CP=1, so during CP=1, the data state of the D terminal changes without affecting the output state of the flip-flop.
D flip-flops are widely used and can be used for digital signal registration, shift registering, frequency division and waveform generators.
I accidentally saw some well-known companies' pen test questions, and scanned them randomly. I saw several questions about FPGA/CPLD, small programming problems, using VerilogHDL or VHDL language to edit triggers, my head turned a bit, and the blur seemed to Clear, clear and immersed in blur, huh, huh. . . In the first half of the year, due to the Boss project, I learned the FPGA, and I was a little anxious to learn, and it was intermittent. It took only a few months. It seems that the knowledge has gone away, the computer is turned on, the previous information is quickly viewed, and the memory is back. . . Simply record this question, the right to remember. . .
/ / Basic D trigger
Module D_EF(Q,D,CLK)
Input D, CLK;
Output Q;
Reg Q; //The signal assigned in the always statement is declared as a reg type register definition
Always @ (posedge CLK) // rising edge, falling edge is represented by negedge, ^_^ requires memory
Begin Q <<= D; end
Endmodule
/ / D flip-flop with asynchronous clear 0, asynchronous set 1
Module D_EF(q,qn,d,clk,set,reset)
Input d,clk,set,reset;
Output q,qn;
Reg q,qn;//register definition
Always @ (posedge clk or negedge set or negedge reset)
Begin
If(!reset) begin q“=0;qn“=1; end//asynchronous clear 0, low effective
Else if(!set) begin q "=1; qn "=1; end // asynchronous set, low effective
Else begin q "=~d;qn"=~d;end
End
Endmodule
/ / D flip-flop with synchronous clear 0, synchronous set 1
Module D_EF(q,qn,d,clk,set,reset)
Input d,clk,set,reset;
Output q,qn;
Reg q,qn;
Always @ (posedge clk)
Begin
If(reset) begin q"=0;qn"=1;end//sync clear 0, high effective
Else if(set) begin q"=1;qn"=1;end //sync set to 1, high effective
Else begin q "=~d;qn"=~d;end
End
Endmodule
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