FPGA Learning Series: 6. Combinational Logic and Sequential Logic

design background:

Verilog HDL language is divided into two kinds of general-oriented and simulation-oriented statements, and synthesizable sentences are far less than the simulation statements, the reader may have a relatively simple feeling of comprehensive design. However, the fact is just the opposite. This is because: First of all, the synthesizable design is used to build the hardware platform. Therefore, the indicators of the design are very demanding, including resources, frequency and power consumption, which need to be reflected by code; In the actual development, the use of basic Verilog HDL statements to complete a wide range of hardware development, has brought great challenges to designers. All simulation statements exist only for verification of synthesizable designs. In order to provide readers with an in-depth understanding of synthesizable design and flexible use of what has been learned, this chapter will extract the basic knowledge and difficulties in comprehensive design and integrate it into Verilog HDL grammar and development tools. It will explain the design to the reader in a simple and easy way. Difficulties in nature .

 

Design principle :  

The design of this time is mainly used to understand the relationship and the writing method of the combination and the sequential logic. By simulating the combination and the sequential logic circuit to simulate the simulation waveform used, the logic characteristics and the corresponding relationship are analyzed.

 

Design architecture diagram :

 

Design code :

Combinational logic design module

0   Module study ( data_1 , data_2 , data_out );   // Port list

1  

2   Input data_1 , data_2 ;    // Enter

3   Output   Reg data_out ;     // output

4  

5   // Describe a combinatorial logic circuit

6   Always   @   (*)  

7   Begin

8   data_out = data_1 && data_2;   // and logic

9   End

10

11   Endmodule  

 

Test module

0   `timescale   1ns   /   1ps

1  

2   Module tb ;

3  

4   Reg data_1 , data_2 ;    // Define the input register

5   Wire data_out ;          // Define the output line type

6  

7   Study study_dut (         // Design module port instantiation

8   . Data_1 (data_1),  

9   . Data_2 (data_2),

10. Data_out (data_out)

11 );

12

13 initial   Begin          // Describe changes in data flow

14 data_1 =   0 ; data_2 =   0 ;

15 # 200

16 data_1 =   1 ; data_2 =   0 ;

17 # 200

18 data_1 =   0 ; data_2 =   1 ;

19 # 200

20 data_1 =   1 ; data_2 =   1 ;

21 # 200

22 data_1 =   0 ; data_2 =   0 ;

23 # 200

24 $stop ;          //The system task is stopped

25 end

26

27   Endmodule  

 

Combinational logic simulation diagram :

The change sequence of the input data stream can be clearly seen in the simulation waveform. After the data is flipped, the output immediately changes without delay.

 

 

 

Sequential logic design module

0   Module study ( clk , data_1 , data_2 , data_out );   // Port list

1  

2   Input clk , data_1 , data_2 ;    // Enter

3   Output   Reg data_out ; // output

4  

5   // Describe a combinatorial logic circuit

6   Always   @   ( posedge clk )  

7   Begin

8   data_out <= data_1 && data_2;   // and logic

9   End

10

11   Endmodule  

 

Test module

0   `timescale   1ns   /   1ps

1  

2   Module tb ;

3  

4   Reg clk , data_1 , data_2 ;    // Define the input register

5   Wire data_out ;          // Define the output line type

6  

7   Study study_dut (         // Design module port instantiation

8   . clk ( clk ) ,

9   . Data_1 (data_1),  

10. Data_2 (data_2),

11. Data_out (data_out)

12 );

13

14 initial   Begin          // Describe changes in data flow

15 clk =   1 ; data_1 =   0 ; data_2 =   0 ;

16 # 200 .1

17 data_1 =   1 ; data_2 =   0 ;

18 # 200 .1

19 data_1 =   0 ; data_2 =   1 ;

20 # 200 .1

21 data_1 =   1 ; data_2 =   1 ;

22 # 200 .1

23 data_1 =   0 ; data_2 =   0 ;

24 # 200

25 $stop ;          //The system task is stopped

26 end

27

28 always   # 10 clk =   ~ clk ;

29

30   Endmodule  

 

Timing logic simulation diagram :

 

   It can be clearly seen in the simulation that, in the sequential logic, we or the integrated register, that is to say the data obtained will have a rising edge in the register, because it is triggered by a rising edge and is seen in the waveform. When both inputs are high, the output should also be high, but it does not immediately change to high, waiting for the next rising edge to go high.

In this way, the difference between the waveforms synthesized by the combination and the sequential logic is clearly visualized, that is, one of the combinations is a linear type and the other is a register.

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