Is there any way to solve the problem of abundant but wasted standard FPGA resources? Embedded F...

FPGA is known for its fast calculation speed, rich resources, and programmable. It has been used in the field of high-speed digital signals and ASIC verification before. With the enrichment of logic resources and the improvement of programming tools, FPGAs have received more and more attention in machine learning and hardware acceleration. At present, data centers have been widely adopted, and FPGA devices are gradually adopted in the fields of big data and cloud computing. However, in addition to these applications that require high computing power and logic resources, there are many small applications with simple functions on the market. If the existing "large and complete" FPGA products are used, it is not only expensive, but also a waste of resources. So some people thought of customized services, so that engineers can customize suitable FPGA products according to product requirements, so as to achieve the purpose of saving cost and power consumption. Embedded FPGA is expected to solve this problem.

Recently, Achronix launched Speedcore custom blocks for its eFPGA IP solution. According to Steve Mentor, vice president of marketing, “Speedcore custom blocks can greatly improve performance, power consumption, and area efficiency, and support functions that were not previously possible on FPGA stand-alone chips. Using Speedcore custom blocks, Customers can obtain ASIC-level efficiency while maintaining the flexibility of FPGAs, which brings an efficient implementation that can minimize power consumption and area while maximizing data throughput."

FPGA users are guided, standard FPGA not only includes the logic design, various memories, DSP and wiring in the FPGA core, but also includes programmable I/O, SerDes and various interface controllers outside the core, which makes the chip resources rich , But it is bulky and expensive, so unnecessary resources in the design must be cut to achieve cost reduction. Achronix's approach is to carry out two layers of tailoring:

As shown in the figure, the first layer of tailoring tailors the external programmable I/O, SerDes and various interface controllers, leaving only the FPGA core, so the area can be reduced by 50%.

As shown in the figure, after cutting off the peripheral modules, can the FPGA core be further reduced? So, starting from the FPGA core structure analysis, Steve Mentor pointed out, “Microsoft talked about a cloud-scale acceleration architecture in its white paper on the Catapult project, including shells and applications. The shell layout IO and The application is the core logic of logic circuits related to circuit boards, and Shell occupies 44% of the total area."

Achronix performed the second level of tailoring, removing the shell, leaving the Fusion Custom Block custom unit block with user-defined functions, which is included in Speedcore's programmable structure. After this cutting, the chip area is reduced by up to 75%.

How to implement the definition is the most concerned issue of many users. Steve Mentor explained, "Achroinx uses internal tools to analyze customer designs to identify potential functions that can be optimized with Fusion Custom Block unit blocks, such as frequently used repetitive functions, to achieve area reduction, performance improvement, and power consumption. Reduced. Now, after adding Speedcore custom blocks to Achronix eFPGA IP products, it has programmability while also having ASIC-level performance and high chip area efficiency."

Development tools are critical in FPGA design. Achronix also provides ACE design tools, which can fully support Speedcore custom blocks, which can be used in the same way as memory and DSP cell blocks, providing functions from design capture to bitstream production and system debugging. .

Achronix creates a unique graphical user interface (GUI) for each Speedcore custom blocks, which can manage all configuration rules. ACE has complete timing details of all configurations of Speedcore custom blocks, and supports ACE to complete various designs based on timing placement and routing. Customers can use the powerful layout planner to optimize the design, and make local or fixed-point task arrangements for all unit instances. ACE also includes a critical path analysis tool, which can support customers to analyze timing. Customers can also use ACE's powerful Snapshot embedded logic analyzer to create complex triggers and display real-time signals in Speedcore.

Since eFPGA is so flexible, will it replace FPGA in the future? Steve Mentor said, "At present, the market share of standard FPGA is about 80%, and eFPGA is 20%. Some customers with complex applications are willing to add eFPGA to ASIC design, and some customers with simple applications are willing to use eFPGA instead of standard. FPGA completes the design, but the two target customer groups are different and will coexist for a long time."

"It is precisely because of the strong market demand for eFPGA that Achronix achieved strong sales revenue and business growth in 2017, with sales expected to exceed 100 million U.S. dollars. 16nm products made by TSMC and TSMC have been mass-produced, and 7nm products are expected in the first half of 2018. Complete the test chip and the first batch of designs." Steve Mentor added.

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