SoC designed scalable verification solution

To take full advantage of the benefits of system-on-chip (SoC) design, the industry needed an scalable verification solution that addressed all phases of the design cycle and shortened the verification gap. This article explores why scalable verification solutions can and can solve the tough challenges of SoC design's current capabilities to improve design productivity, ensure design quality, reduce time-to-market, and increase return on investment.

Functional verification is one of the main challenges facing electronic designers. To differentiate their products from the competition, more and more functions are being integrated into their products, including analog/mixed-signal content, embedded processing. With their respective software, the overall system has become increasingly complex. As the design achieves size reduction and increased integration, the complexity of verification increases dramatically, and the length and number of test vectors increase. If there are errors in the design, it will become increasingly difficult for people to discover the cause of the error, and the cost of future changes and re-production is also very high.

Functional errors are the primary cause of design re-spinning, which has a negative and negative impact on return on investment and time-to-market. In all chip designs, 60% require at least two re-spins. For all re-spinning designs, 62% were caused by functional errors. Unfortunately, the functional verification method has not experienced any major changes for many years. The verification technology has lagged behind the design and manufacturing capabilities, forming a verification gap, and the gap is still expanding, making the design potential become a confession. . For the same reason, simulation and verification become the bottleneck of the entire design process, creating obstacles to improving design productivity (Figure 1).

In order to solve the verification gap problem and improve the verification level of system-on-a-chip, product managers need to adopt a positive attitude to solve functional verification as an integral part of the overall design method. The most effective way to achieve this goal is to adopt a scalable verification method that can be implemented between different tools and different levels of abstraction. Functional verification strategies must target the entire system, including digital hardware, embedded software, and mixed-signal content, and must take into account each design level and every stage of the design process.

As designs evolve steadily in size and complexity, the importance of functional verification continues to increase. The complexity of the design is mainly reflected in the increasing proportion of embedded software and analog circuits.

Design components are becoming more diverse, and more and more functional components are integrated on a single chip. Diversified components include high-performance RISC CPUs, multi-gigabit high-speed I/O, RAM, system clock management, analog/mixed-signal, embedded software, and dedicated digital signal processors, so the interconnection between these components is overall The impact of functional performance is becoming increasingly important. The interaction between them has become a key point in the verification work. The increased use of on-chip software and analog components has also made system complexity increasingly prominent and poses a challenge to traditional methods of operation. Digital engineers must face and solve their unfamiliar simulation problems. Numerous hardware designs require firmware or low-level software to work properly in order to validate RTL functions. This requires firmware designers to play an important role in hardware design and to resolve hardware and software in a detailed manner. The issue of mutual influence.

The design scale means a huge number of transistors, which is the concept of the number of gates in a system-on-chip. In 2001, the International Semiconductor Group predicted that system-on-chips would contain billions of transistors by 2006, and now a system-on-a-chip has reached tens of millions of gates. The increase in design size means that the possibility of error increases, and the complexity of the verification task is increasing at the speed of the exponential function.

A single tool or a single technology cannot solve the verification problems that are currently faced in an appropriate way, because these tools are optimized for a specific object in the design process, even the hardware description language (HDL). The simulation engine also requires multiple solutions. Some solutions work better at the module level, while others perform better at the chip or system level. Therefore, the design team needs to form a complete solution from RTL simulation to online simulation to formal verification through a set of tools that can work together, which requires various verification techniques to solve the increasingly prominent design in breadth and depth. Verification challenges due to size, complexity, and performance issues.

The extensible verification solution must support all major languages, including Verilog, VHDL, C++, and SystemC, so that it can work at all levels of abstraction. It must be a solution that uses open standards to follow and leverage existing and third-party verified IPs. Verification tools can also be selected with their own characteristics, not because they are suitable for the tool environment of a particular EDA vendor. An ideal work environment must be able to handle a variety of different design languages ​​and support the industry's key standards to ensure that existing designs and test benches can be reused.

In order to address the growing problem of shrinking design size, complexity, and performance, verification methods must be able to scale between different tools and design levels. It also needs to scale between the various verification domains and communicate between simulation, co-verification, simulation, and analog-to-digital hybrid simulation. In addition, it is dynamically adaptable and free to expand. For example, the introduction of formal equivalence checking tools is a requirement of ultra-large-scale design, especially for many modified designs on gate-level netlists.

It is also necessary for the tool itself to be scalable, as different types of verification methods cover different performance ranges and provide different solutions. Every solution must compromise between verifying integrity and performance. For example, designers need to use advanced verification tools for verifying system-level DSP algorithms, and using HDL simulators for such tasks will not work. Conversely, for the sub-module verification problem in the chip design that the HDL simulator can quickly solve, it is not very appropriate to use the live emulation verification. Recognizing which tools are the best choice for performing current verification tasks and getting these tools will give designers the best performance. The following are alternatives that designers can use to develop a digital design verification process:

Software simulation: Ideal for module-level verification because of its very fast conversion and error correction capabilities.

Software and hardware co-simulation: The ability to bring embedded software into the verification environment provides a way to speed up processor, memory, and bus operation verification. It can also be used to provide incentives for hardware verification at the test bench.

Collaborative modeling (task-based accelerated simulation): It has the flexibility of software test bench and the high performance of simulation, providing a rich solution for system verification. Collaborative modeling and simulation is an ideal bridge to connect the high-level abstract test platform with the entire chip RTL implementation.

In-line emulation: It provides high-capacity and high-performance verification in real-world systems. Emulation gives designers enough information to confident that their chips will function properly in real-world systems.

Formal Verification/Equivalent Check: It has the necessary capacity and speed to ensure that netlist modifications made later in the design process do not change their functional and behavioral characteristics.

It is important to point out that hardware-assisted or hardware-oriented high-performance verification solutions are critical to our ability to achieve verification integrity at the system level, and field-like validation can completely avoid costly design duplication.

The scalability between the various levels of abstraction is equally important. As verification operations become more abstract, the level of abstraction of simulation models and task processors increases, and early verification by engineering teams can have a constructive impact on design decisions. Abstract work speeds up verification by eliminating all irrelevant information, shortens development time, speeds up error correction, and makes the test platform more reusable.

An important reason for doing abstract work is that in the case of complex system-on-chip, it takes too much time to do all of this at the RTL or gate level, and the difficulty is too great to be realized. It is recognized that it is absolutely necessary to adopt a higher level of abstract representation in the design. This work is not only for the design process, but also for the construction of the test platform.

In order for this multi-level abstraction strategy to work, it is not enough to have the necessary tools. The accumulation of IP is equally important. If you don't let the designer build a model that switches between abstract levels of abstraction and links the levels of abstraction, then simulation techniques that allow multiple levels of abstraction will be useless. A multi-abstract level verification solution combines technology and intellectual property.

Hierarchical verification is possible when a set of task processors is used as the basic interface for design. This allows for the merging of different levels of design abstraction, assembling into a test platform or verification environment to check whether an implementation can be consistent with higher level abstract model functionality. The advantage of this verification strategy is that it does not require all models to exist in a single level of abstraction, and its flexibility allows the team to obtain a verification platform that is fused by different levels of abstraction within a defined time frame.

Then extract a single level or a single module within the system (or use the IP necessary to perform task processing) to replace them with a more specific implementation level. They can be run as an instant test platform in the system, and the design team can immediately introduce it into the existing test platform to provide real verification incentives to the sub-module. The result is that the verification efficiency and verification quality of the design are guaranteed.

A task-based interface can provide a link between all abstract system models and the design, providing an ideal system-level test platform. Using collaborative modeling and simulation technology and online simulation verification technology, it can also run system-level verification environment based on task processing at high speed. The verification speed can meet the error rate in wireless data transmission design, and can directly observe the video processing of MPEG design. The effect, as well as running the application code directly in the verification environment.

We believe that verification requires a scalable verification solution that addresses the complexity of digital, analog, and software content and must support different levels of abstraction throughout the electronic system.

• Module level: At the module level, the designer's focus is on the verification of functions and timing details to ensure that these modules meet the technical specifications, no obvious problems exist. The goal is to find as many design errors as possible, because module-level verification is the lowest and most efficient phase of finding and correcting these errors. The interaction between analog and digital circuits should also be verified at the module level. During this phase, the various functions and code will be fully implemented and the verification sign-off will be completed. The HDL simulator is an ideal tool at this stage because it is easy to use and has the ability to correct errors.

Analog/Mixed-Signal Modules: The number of system-on-chip designs using analog and mixed-signal components is increasing, requiring analog-environment-proven environments to perform the same verification functions as functional verification of digital circuits. With Mentor's ADVance MS Validation Suite tool, ModelSim provides a smooth interface for simulating HDL behavioral simulation and SPICE simulation of analog modules. This interface allows simultaneous processing and viewing of simulations of digital and analog events in the same error correction environment. The ADVance MS simulator provides a single-core verification environment for verification of complex analog/mixed-signal designs.

Subsystem level: After all modules have been fully verified, they will enter the module integration phase, with multiple modules forming higher level modules and even the entire chip integration. In the subsystem verification phase, inter-module communication, control, timing, and protocol implementation are important to ensure the correctness of the subsystem's functionality; therefore, it is useful to perform protocol checks or assertions to verify bus data exchange tools. . Hardware accelerated simulation tools or emulation verification tools can be configured at this stage, and their verification test platforms can be implemented in other advanced verification languages ​​such as HDL, C, System C, and Verisity.

System-on-chip level: Chip-level verification involves further integration of the various modules and the rest of the design flow, such as the design of embedded software and the physical implementation process. In the process of designers integrating smaller modules into larger and larger modules, more and more simulations are needed, running time is getting longer, design verification requires more simulation work, and multiple verification tasks are proposed. Requirements, such as functional testing of the chip and system, verification of the integrated design and post-route results, verification of the synthesis or routing tool processing did not change any behavioral characteristics of the design.

At this level of verification, equivalent checks, hardware emulator arrays, or emulation verification tools can also be used to ensure that the entire design does not change any of the design's features during back-end processing—this is often referred to as regression testing. The use of hardware emulator arrays provides users with higher data throughput and a complete solution for smaller test vector tests. Imitation verification tools (such as VstaTIon) are recommended for larger test vector tests because of their ability and capacity to validate large-scale chip designs. Hardware simulator arrays and simulation verification tools are complementary solutions that can be used effectively in different application environments.

Most system-on-chips use embedded software, which must be verified. Embedded software includes application code, real-time operating systems, device drivers, hardware diagnostics, and self-starting ROM programs. Functionality is an important factor at this stage, but data throughput and other system-level performance issues must also be taken seriously. We apply hardware and software error correction tools as well as hardware acceleration and simulation to ensure that the chip achieves normal functionality and performance characteristics.

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