Design and Implementation of a Multi-Axis Motion Controller Based on STM32 and FPGA

The numerical control system has been widely used in the industrial and mining field. The computer numerical control system realizes the control of the motor by controlling and calculating the digital information and converting it into a pulse signal, thereby controlling the operation of the numerical control machine tool and the machining of the parts. With the development of embedded technology, we can design a smaller, lower cost, more specific embedded system to complete the work done by traditional computer numerical control systems.

The system is based on the embedded processor STM32 and FPGA chip, and the processing part of the motion control scheme is implemented in the FPGA. This is a hardware softening solution, which has the characteristics of software programmable, reconfigurable, high performance, high reliability and high consistency. The system block diagram is shown in Figure 1.

Figure 1 System principle

STM32 reads the data file from the SD card and performs related algorithm processing. The initial speed, maximum speed, initial value of acceleration and some control parameters of the system acceleration and deceleration are set by the keyboard scanning circuit. The corresponding parameters are transmitted to the FPGA for processing. Finally, the FPGA controls the output pulse and the inter-pulse delay, and is output by the high optocoupler isolation to control the operation of the motor. Through RS232 to achieve data communication with the host computer and drive the LCD to complete the human-computer interaction. FPGA is mainly used to implement motion control algorithms such as command and data processing modules, acceleration and deceleration modules, and interpolation function modules (including linear interpolation and circular interpolation).

In order to avoid over-travel, impact, out-of-step and oscillation of each axis during start-up, operation and speed change, the smooth and accurate positioning of the moving mechanism is guaranteed, which requires the motor to have a transfer in each block. The process of acceleration and deceleration makes it a smooth transition. Most motion control systems have trapezoidal acceleration and deceleration and S-type acceleration and deceleration. Due to the simple trapezoidal acceleration and deceleration algorithm, fast system response and high efficiency, combined with the main problems to be solved in this topic and related fields of application, the subject is improved on the basis of traditional trapezoidal acceleration and deceleration to realize pulse output. The trapezoidal acceleration/deceleration algorithm uses the pulse superposition method to realize the internalization of the FPGA, that is, based on a certain clock, it is divided into n times to generate n kinds of pulses of different frequencies that do not overlap each other, and then extract the required numbers. The pulses are superimposed by equation (1) to output continuously adjustable pulses of different frequencies to complete the acceleration and deceleration operations. Equation (1) is as follows:

It can be seen from equation (1) that f0/2n is a frequency division of the reference pulse, and the number of bits of the frequency division counter is set in the frequency division process to generate pulses of different frequencies and not overlapping. The coefficient a[N:0] is the number of pulses generated per unit time, that is, the pulse rate. It can be concluded that the circuit diagram of the system logic structure under the method is as shown in Fig. 2.

Figure 2 system logic structure circuit

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