Must Read: Summary of Embedded System Foundation and Knowledge and Interface Technology
This article mainly introduces some basic knowledge of embedded systems, from the embedded system foundation, including the definition of embedded systems, the composition of embedded systems, real-time systems, logic circuit infrastructure and interface technology, I hope to help you.
Embedded system foundation
1. Definition of embedded system
(1) Definition: Application-oriented, based on computer technology, software and hardware can be tailored to meet the application system's special computer system with strict requirements on function, reliability, cost, size and power consumption.
(2) Four stages of embedded system development: no operating system stage, simple operating system stage, real-time operating system stage, and Internet-oriented stage.
(3) Intellectual property core (IP core): A functional module that has intellectual property rights, specific functions, interface specifications, and can be reused in multiple integrated circuit designs, and is a basic component for implementing a system-on-chip (SOC).
(4) The IP core module has different levels of behavior, structure and physics. The corresponding description of the functional behavior can be divided into three categories: soft core, solid core and hard core.
2, the composition of the embedded system
Includes: hardware layer, middle layer, system software layer and application software layer
(1) Hardware layer: embedded microprocessor, memory, general device interface and I/O interface.
Embedded core module = microprocessor + power circuit + clock circuit + memory
Cache: Located between the main memory and the embedded microprocessor core, it stores the most frequently used program code and data from the microprocessor. Its main goal is to reduce the memory access bottleneck caused by memory to the microprocessor core, making processing faster.
(2) Middle layer (also known as hardware abstraction layer HAL or board support package BSP).
It separates the upper layer software of the system from the underlying hardware, so that the upper layer software developers of the system do not need to be related to the specific conditions of the underlying hardware, and can develop according to the interface provided by the BSP layer.
BSP has two characteristics: hardware dependencies and operating system dependencies.
Designing a complete BSP requires two parts to be done:
A. Hardware initialization and BSP functions of the embedded system.
Chip-level initialization: pure hardware initialization process, the embedded microprocessor is gradually set from the default state of power-on to the working state required by the system.
Board-level initialization: The initialization process, which consists of two parts, software and hardware, to establish the hardware and software operating environment for subsequent system initialization and application.
System level initialization: A software-based initialization process that initializes the operating system.
B. Design hardware-related device drivers.
(3) System software layer: It consists of RTOS, file system, GUI, network system and common component modules.
RTOS is the foundation and development platform for embedded applications.
(4) Application software: consists of applications developed based on real-time systems.
3, real-time system
(1) Definition: A system that can perform system functions and respond to external or internal, synchronous or asynchronous time within a specified or determined time.
(2) Difference: The general system generally pursues the average response time of the system and the user's convenience; while the real-time system mainly considers the system behavior in the worst case.
(3) Features: time constraint, predictability, reliability, and interaction with the external environment.
(4) Hard real-time (strong real-time): It means that the time requirement of the application should be fully satisfied, otherwise it will cause major security accidents and even cause major loss of life and property and ecological damage, such as: aerospace and military.
(5) Soft real-time (weak real-time): Although some applications have time requirements, real-time tasks occasionally violate this requirement and will not have serious impact on system operation and environment, such as monitoring system and real-time information collection system.
(6) Task constraints include: time constraints, resource constraints, execution order constraints, and performance constraints.
4, real-time system scheduling
(1) Scheduling: Given a set of real-time tasks and system resources, determine the entire process of when and where each task is executed.
(2) Preemptive scheduling: usually priority-driven scheduling, such as uCOS. The advantage is that the real-time performance is good, the response is fast, the scheduling algorithm is relatively simple, and the time constraint of the high-priority task can be guaranteed; the disadvantage is that there are many context switches.
(3) Non-preemptive scheduling: Usually scheduled by time slice, the task is not allowed to be interrupted during execution. Once the task occupies the processor, it must be executed or voluntarily given up, such as WinCE. The advantage is that the context switching is less; the disadvantage is that the processor has low effective resource utilization and poor schedulability.
(4) Static table driving strategy: Before the system runs, according to the time constraints and associations of each task, a certain search strategy is used to generate a running time table, indicating the starting running time and running time of each task.
(5) Priority driving strategy: Determine the execution order of tasks according to the priority of the task.
(6) Real-time task classification: periodic tasks, incidental tasks, and non-periodic tasks.
(7) General structure model of real-time system: data collection task realizes sensor data collection, data processing task processes the collected data, and sends the processed data to the execution organization management task control organization for execution.
5, embedded microprocessor architecture
(1) von Neumann structure: program and data share a storage space, program instruction storage address and data storage address point to different physical locations of the same memory, using a single address and data bus, the program and data have the same width. For example: 8086, ARM7, MIPS...
(2) Harvard structure: Program and data are two independent memories. Each memory is independently addressed and accessed independently. It is a memory structure that separates program storage from data storage. For example: AVR, ARM9, ARM10...
(3) Comparison of the characteristics of CISC and RISC.
The time P required by the computer to execute the program can be calculated using the following formula:
P=I&TImes;CPI&TImes;T
I: The number of instructions that are run on the machine after the high-level language program is compiled.
CPI: The average number of cycles required to execute each instruction.
T: The time of each machine cycle.
(4) The idea of ​​the pipeline: Sub-processes in which the serial execution of an instruction is changed into several instructions in the CPU are executed in the CPU.
(5) Indicators of the assembly line:
Throughput rate: The number of results from the line processor in a unit of time. If the sub-process of the pipeline takes a different amount of time, the throughput rate should be the reciprocal of the longest sub-process.
Settling time: The time at which the pipeline starts working to reach the maximum throughput rate. If the time used by m sub-processes is the same, both are t, then the time T=mt is established.
(6) Byte order of information storage
A, memory unit: byte (8-bit)
B. The word length determines the addressing capability of the microprocessor, that is, the size of the virtual address space.
C, 32-bit microprocessor virtual address space bit 232, which is 4GB.
D, little endian byte order: the low byte is at the low address of the memory, and the high byte is at the high address of the memory.
E, big endian byte order: the high byte is at the low address of the memory, and the low byte is at the high address of the memory.
F. The storage order of network devices depends on the data link layer in the bottom layer of the OSI model.
6, the logic circuit foundation
(1) According to whether the circuit has a storage function, the logic circuit is divided into: a combinational logic circuit and a sequential logic circuit.
(2) Combinational logic circuit: The output of the circuit at any time depends only on the input signal at that moment, regardless of the state of the circuit before the input signal is applied. Commonly used logic circuits include decoders and multiplexers.
(3) Sequential logic circuit: The output of the circuit at any time is not only related to the input at that moment, but also related to the state of the circuit at that moment. Therefore, memory elements must be included in the sequential circuit. Triggers are the basis for constructing sequential logic circuits. Commonly used sequential logic circuits include registers and counters.
(4) The concept of truth table, Boolean algebra, Morgan's law, and gate circuit.
(5) NOR (or non-) and NAND (NAND) gates are called full-featured gates and can implement any kind of logic function.
(6) Decoder: A combined logic network with multiple inputs and multiple outputs.
Each time an n-bit binary code is entered, at most one of the m outputs is valid.
When m=2n is, it is fully decoded; when m is 2n, it is partially decoded.
(7) Since the high-level output current of the integrated circuit is small, and the low-level output current is relatively large, when the integrated gate circuit directly drives the LED, the low-level driving mode is often used. The liquid crystal seven-segment display LCD utilizes different optical characteristics of the liquid crystal with an applied electric field and no external electric field to display characters.
(8) The clock signal is the basis of the timing logic and is used to determine the appropriate update of the state in the logic unit. Synchronization is the main constraint in clock control systems.
(9) When selecting a trigger, the trigger mode is a factor that must be considered. There are two ways to trigger:
Level trigger mode: It has a simple structure and is often used to form a scratchpad.
Edge trigger mode: It has strong anti-data interference capability and is often used to form registers, counters, etc.
7, bus circuit and signal drive
(1) The bus is a collection of various signal lines and is a common path for transferring data, addresses, and control information between components in an embedded system. At the same time, one binary signal can be transmitted on each path. According to the type of information transmitted by the bus, it can be divided into: data bus (DB), address bus (AB) and control bus (CB).
(2) Main parameters of the bus:
Bus bandwidth: The amount of data that can be transferred on the bus within a certain period of time, generally expressed in MByte/s.
Bus width: The number of bits of data that the bus can transmit at the same time, that is, the concept of bus widths such as 32-bit and 64-bit, which is often referred to as bus width. The wider the bit width of the bus, the larger the data transfer rate per second of the bus, that is, the wider the bus bandwidth.
Bus frequency: The working clock frequency is in MHz. The higher the operating frequency, the faster the bus operates, that is, the wider the bus bandwidth.
Bus Bandwidth = Bus Bit Width & TImes; Bus Frequency / 8, in MBps.
Common bus: ISA bus, PCI bus, IIC bus, SPI bus, PC104 bus and CAN bus.
(3) Only devices with three-state outputs can be connected to the data bus. The commonly used tri-state gates are output buffers.
(4) When the load connected to the bus exceeds the load capacity of the bus, a buffer or driver must be added between the bus and the load. The most commonly used is a tristate buffer, which functions to drive and isolate.
(5) The bus bus multiplexing technology can realize the sharing of the data bus and the address bus. But it will bring two problems:
A. It is necessary to add an external circuit to multiplex and decouple the bus signal, for example: an address latch.
B. The bus speed is lower than that of the non-multiplexed bus system.
(6) Two types of bus communication protocols: synchronous mode and asynchronous mode.
(7) The solution to the bus arbitration problem is based on the concept of priority (priority).
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