Unusual breaks in the ARM system and how to deal with them

In the ARM system, there are usually 3 ways to control the execution flow of the program:

• During normal program execution, the value of the program counter register (PC) is incremented by 4 bytes for each execution of an ARM instruction, and the value of the program counter register (PC) is incremented by 2 bytes for each execution of a Thumb instruction. The entire process is performed sequentially.

• With a jump instruction, the program can jump to a specific address label for execution, or jump to a specific subroutine for execution. Among them, the B instruction is used to perform the jump operation; the BL instruction is to save the return address of the subroutine while executing the jump operation; while the BX instruction is performing the jump operation, the state of the program can be switched to the lowest position of the target address. Thumb state; BLX instruction performs 3 operations: jump to the target address to execute, save the return address of the subroutine, according to the lowest bit of the target address can switch the program state to Thumb state.

• When an abnormal interrupt occurs, the system will jump to the corresponding abnormal interrupt handler after executing the current instruction. When the execution of the abnormal interrupt handler is completed, the program returns to execution at the instruction next to the interrupted instruction. When entering the abnormal interrupt handling program, the execution site of the interrupted program is saved, and when the abnormal interrupt processing program exits, the execution site of the interrupted program is resumed.

Abnormal interrupt types in the ARM system:

• Reset: When the reset pin of the processor is valid, the system generates a reset abnormal interrupt and the program jumps to the reset abnormal interrupt handler. The reset abnormal interrupt is usually used in the following two situations: when the system is powered on and when the system is reset. Jump to reset interrupt vector execution, known as soft reset.

• Undefined Instruction: An undefined instruction abort occurs when the ARM processor or coprocessor in the system considers the current instruction undefined.

• Software Interrupt SWI: This is a user-defined interrupt instruction. Programs that can be used in user mode invoke privileged operation instructions. In real-time operating systems, system function calls can be implemented through this mechanism.

• Prefetch Abort: If the address of a processor-prefetched instruction does not exist, or the address does not allow access to the current instruction, when the prefetched instruction is executed, the processor generates an instruction to prefetch the aborted interrupt. .

• Data Abort: If the target address of a data access instruction does not exist, or if the address does not allow access by the current instruction, the processor generates a data access abort exception interrupt.

• External interrupt request (IRQ): The processor generates an external interrupt request (IRQ) exception interrupt when the processor's external interrupt request pin is asserted and the ISR control bit in the CPSR register is cleared. Each peripheral in the system usually services the processor through this exception interrupt.

• Fast Interrupt Request (FIQ): When the processor's external fast interrupt request pin is asserted and the F control bit of the CPSR register is cleared, the processor generates an external interrupt request (FIQ) exception interrupt.

The process of responding to abnormal interrupts (these are the actions that the ARM core has already completed):

• Save the current processor status, interrupt mask bits, and condition flags as. This is achieved by saving the contents of the current program status register CPSR in the SPSR register corresponding to the abort interrupt to be executed. Each abnormal interrupt has its own physical SPSR register.

• Set the corresponding value in the current program status register CPSR. Including: setting the bits in the CPSR to enable the processor to enter the current corresponding execution mode (processor mode); setting the bits in the CPSR to disable the IRQ interrupt; when entering the FIQ mode, the FIQ interrupt is disabled.

• Set the register lr_mode to the return address.

• Set the program counter value (PC) to the interrupt vector address of the abort, and jump to the corresponding abort handler for execution.

Return from exception handlers (these return actions need to be written by the code itself):

• Resume the processor state of the interrupted program by copying the contents of the SPSR_mode register to the CPSR.

• Return to the next instruction execution of the instruction that caused the abort, that is, copy the contents of the lr_mode register to the program calculator PC.

The reset exception interrupt handler does not need to return. The resetting of the abnormal interrupt handler starts the execution of the entire user program so that it does not need to return.

6V Dc Vibration Motor

Vibration Motor is in the original basis to add a vibrating head, made into a Dc Motor drive with a vibration motor. To produce the shaking force.

6V Dc Vibration Motor is introduced:

6V Dc Vibration Motor volume is generally greater than 15 mm, mainly used in massage chair, massage waist, handheld massager, etc.

Characteristics: small volume, strong vibration;

Features: small size, fast speed, stable performance, low price, can use battery drive,Can change the different materials of the pendulum head

Method of use: the best stable in horizontal plane, installed on the dc 6V Dc Vibration Motor output shaft parts, cannot use a hammer to knock, knock prone to press into the dc 6V Dc Vibration Motor drive, may cause damage to internal components, and cannot be used in the case of blocked.

Operating temperature range:

6V Dc Vibration Motor should be used at a temperature of -10~60℃.

The figures stated in the catalog specifications are based on use at ordinary room temperature catalog specifications re based on use at ordinary room temperature (approximately20~25℃.

If a vibration motor is used outside the prescribed temperature range,the grease on the gearhead area will become unable to function normally and the motor will become unable to start.Depending on the temperature conditions ,it may be possible to deal with them by changing the grease of the motor's parts.Please feel free to consult with us about this.

Storage temperature range:

Dc Vibration Motor should be stored ta a temperature of -15~65℃.

In case of storage outside this range,the grease on the gearhead area will become unable to function normally and the motor will become unable to start.

Service life:

●Use with a load that exceeds the rated torque

●Frequent starting

●Momentary reversals of turning direction

●Impact loads

●Long-term continuous operation

●Forced turning using the output shaft

●Use in which the permitted overhang load or the permitted thrust load is exceeded

●A pulse drive ,e.g.,a short break,counter electromotive force,PWM control

●Use of a voltage that is nonstandard as regards the rated voltage

●Use outside the prescribed temperature or relative-humidity range,or in a special environment.

●Please consult with us about these or any other conditions of use that may apply,so that we can be sure that you select the most appropriate model.

when it come to volume production,we're a major player as well .each month,we rurn out 600000 units,all of which are compliant with the rohs directive.Have any questions or special needed, please contact us, we have the engineer group and best sales department to service to you Looking forward to your inquiry. Welcome to our factory.

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Shenzhen Shunchang Motor Co., LTD. , https://www.scgearmotor.com