Analysis of DSP's high-speed laser marking control system
The galvanometer scanning laser marking technology is to change the propagation direction of the laser by controlling the deflection angle of two high-speed galvanometers, and then focus on the surface of the workpiece through the F-Theata lens to mark the surface of the workpiece. Compared with traditional marking technology, it has a wide range of applications (suitable for processing surfaces of different materials and shapes), no mechanical deformation of the workpiece, no pollution, fast marking speed, good repeatability, and high degree of automation. It has a wide range of applications in many fields such as national defense and scientific research. High-speed and high-precision galvanometer marking has become the development direction of today's marking industry.
The traditional galvanometer marking control system is connected to the single-chip control board through the PC serial port and parallel port ISA bus. This method has simple interface, convenient connection and low development cost. However, due to the low transmission speed, it can no longer meet the real-time requirements of modern CNC systems. Sexual requirements. This article has made some new explorations in laser marking control technology: using PCI's high-speed data transmission and DSP high-speed data processing capabilities, a "PC + PCI bus + DSP control board" method is proposed for galvanometer marking. The control system realizes precise control of marking control, improves control efficiency, and guarantees the real-time performance of the system. The DSP control board is the core of the entire system, which directly determines the scanning speed and scanning accuracy of the system. This article will focus on the design of the control board.
1 DSP chip
The main chip of the DSP control board is the high-speed data processing chip TMS320C6205 of Texas Instruments C6000 series. The chip is a high-performance fixed-point processor with a main frequency of 200MHz, 8 32-bit instructions per cycle, and a processing speed of 1600MIPS; it adopts a high-performance VLIW structure of TMS320C62xTM DSP core, with 8 independent 32-bit general-purpose registers; provide 64K bytes of internal program RAM and 64K bytes of internal data RAM; provide 32-bit external memory seamless interface, including synchronous devices (such as SDRAM, SBSRAM, etc.), Asynchronous devices (such as FLASH, SRAM, etc.) and addressable 52M bytes of external storage space; provide flexible PLLs, clock generators, and configurable frequency multipliers; provide PCI bus interfaces that comply with PCI 2.2 specifications to directly implement chip and PCI bus bridging function; provides two 32-bit timers; provides JTAG boundary scan interface for online debugging. With this chip, high-speed data processing can be realized, and the real-time performance of the system can be guaranteed. With the PCI bridge function, it provides an interface with the PCI bus, which is economical and reliable.
2 hardware design
2.1 Structural block diagram
Figure 1 shows the block diagram of the hardware structure of the system. The DSP control board is connected to the PC through the PCI bus to realize high-speed communication. The DSP processing module is the main control module, and the TMS320C6205 chip with a main frequency of 200MHz is used as the main control chip. The DSP processing module makes full use of the fast calculation capabilities and high-precision timers of the C6000 series DSP, which can ensure that the galvanometer marking machine performs uniform and high-speed marking, which cannot be done by a PC. The peripheral circuit of DSP includes storage module, reset control, power control, clock system, JTAG port, digital-to-analog conversion module, CPLD logic control module and photoelectric isolation module. The storage modules include FLASH modules and SDRAM modules. FLASH is used to store system startup codes and software codes, and SDRAM is used to provide additional storage space required for software operation. The DSP control board card outputs two analog signals to control the movement of the two galvanometers, outputs a Q switch control signal to control the switching light of the laser, and inputs/outputs 16 photoelectric isolation signals for function expansion.
2.2 Communication between PC and DSP
The PCI bus is a local bus that is not attached to a specific processor. From the structural point of view, PCI is a primary bus inserted between the CPU and the original system bus. Specifically, a bridge circuit realizes the management of this layer, and realizes the interface between the upper and lower to coordinate the transmission of data. The manager provides a signal buffer to enable it to support 10 kinds of peripherals and maintain high performance at a high clock frequency. The PCI bus also supports bus mastering technology, allowing smart devices to obtain bus control when needed to speed up data transmission. Compared with the ISA bus, the PCI bus has the advantages of faster transmission speed and large transmission volume.
This system selects TMS320C6205. This chip comes with PCI bus bridging function that meets the PCI2.2 specification. Developers eliminate the hardware and software implementation of the PCI protocol, which brings convenience to the system design, shortens the development cycle, and saves R & D expense. Developers only need to directly connect the bus signal on the PCI slot with the relevant PCI bus signal on the DSP chip. The DSP control board with "golden finger" can be directly inserted into the PCI card slot of the PC and used to realize the communication between the PC and the DSP. PCI devices can access all internal RAM space, peripherals, and external memory space.
The PCI bus width used by the DSP control board is 32 (3.3V), the bus frequency is 33MHz, and the transmission rate is 33×32/4MB/s = 132MB/s. This transmission rate provides a guarantee for the entire system to achieve high-speed operation.
2.3 CPLD logic control
The logic control of the entire high-speed system is realized through the high-speed CPLD chip. It is realized by using MAX7128E chip of ALTERA company. The available programmable logic gate is 2500, the number of macrocells is 128, the number of logic array blocks is 8, the user can define 100 I/O pins, and the pin-to-pin delay is 5ns. MAX7000 series devices can be programmed through a programmer or online programming. This design uses online programming (ISP). ISP allows rapid and convenient re-programming in the design and development process, simplifies the manufacturing process, and allows devices to be assembled on the printed circuit board before programming.
In the system design, LED signal lights, FLASH, DA chip, 16-channel I/O photoelectric isolation interface, analog switch, Q switch, PWM output, and software reset control all use the address of CE1 space. In order to prevent these devices from interfering with each other, they must Enter the address for decoding. By judging the PA[2:6] and PA[16:21] input to the CPLD, you can know the address area that the DSP is accessing, and perform the address decoding in the CE1 space, thereby generating the corresponding control signal to achieve logic control and timing control .
The high addresses of the registers constructed on the CPLD are all the same, named dsp_reg_addr, composed of Pa16 "21, if Pa16" 21 is set to "111000", it means the address is 0x0178xxxx.
The low address is composed of Pa2 "6, addressing 10 registers, and the address correspondence is shown in Table 1.
Table 1 Address allocation table
2.4 Digital-to-analog conversion module
The digital-to-analog conversion module converts the digital signal processed by the DSP into an analog signal to control the deflection of the two galvanometers. Because the requirements for marking accuracy are getting higher and higher, the traditional 8-bit digital-to-analog converter can no longer meet the needs of users, so this system selects the 16-bit high-precision digital-to-analog converter AD669 chip, as shown in Figure 2. AD669 is a 16-bit parallel input with a secondary data cache structure. In the design, the /L1 signal is directly grounded to be effective, and the first level cache and the second level cache are respectively controlled by controlling the /CS and LDAC signals. The voltage range of the control galvanometer signal is -10V～+10V. Taking a sign with a size of 100mm×100mm as an example, the accuracy can reach 100mm/216=0.0015mm, and the corresponding minimum output voltage is 0.00031V.
Experiments have found that the output of the AD669 chip is an uncontrollable amount when power is on, which will cause the galvanometer to deflect at the moment of power on. If the deflection amplitude is too large, long-term use will cause the galvanometer to break. In order to protect the galvanometer, an analog switch circuit can be designed to control the output of the AD669 chip when it is powered on to make it 0V. The author puts the analog switch on the reference voltage input end of the AD669 chip, and realizes the control of the analog switch through CPLD to control the presence or absence of the reference voltage, so as to ensure that the galvanometer does not deflect when it is powered on.
3 PCB design
The control board uses a high-speed DSP processing chip with a main frequency of 200MHz. In the high-speed signal system, EMC problems exist, which will affect the performance of the system. In order to design a stable control board with good anti-interference performance, the following measures have been taken
1. Reasonable arrangement of layers
The control board is a six-layer board, and the board layers are designed (from the top layer to the bottom layer) signal layer-ground layer-power layer-signal layer-ground layer-signal layer. This arrangement of the board layer structure makes each signal layer and power layer adjacent to a ground layer, providing a short return path for the signal.
2. Processing of the clock signal line
Half of the PCI clock signal needs to be boosted by reflected waves. Therefore, the length of the clock signal CLK trace is approximately 2500 mils, which is realized by a serpentine line (this point is clearly specified in the trace requirements of the PCI2.2 specification). For DSP chips, the crystal oscillator circuit should be as close as possible to the DSP chip, and the clock signal should be as short as possible.
3. Processing of SDRAM related signal lines
The operating frequency of SDRAM is 100MHz. At high frequencies, the signal transmission time is directly related to the signal trace length, and this problem cannot be ignored. Therefore, the data line and address line of the SDRAM should be routed with equal length to ensure the quality of signal transmission. In addition, crosstalk and ringing problems are also very easy to occur at high frequencies. For the control signals and data and address bus signals of the SDRAM and DSP interfaces, matching resistors are connected in series at the source to improve the signal transmission quality and ensure that the SDRAM is at high frequencies. Can work normally.
4. Isolation treatment of digital-analog circuit
There are digital and analog circuits on the control board. When layout, the isolation of digital and analog circuits must be considered. Try to layout the digital and analog circuits in blocks to avoid digital signal traces crossing the analog circuit area to prevent two circuits Mutual interference between. In addition, the digital circuit and the analog circuit share a common ground through a 0 ohm resistor.
5. The use of capacitors
Place a 1.01uF decoupling capacitor next to the power pin of each digital chip.
4 summary
This system combines the high-speed PCI bus with the C6000 high-speed DSP processor, and is equipped with a high-precision digital-to-analog conversion module to realize a high-speed and high-precision control system, and successfully applies it to the galvanometer laser marking system. The system makes full use of the high-speed processing capabilities of DSP and internal high-precision timers, and shares the real-time tasks of the PC, thereby realizing the complementary advantages of the PC and the DSP control board, realizing real-time marking and ensuring marking Uniformity of quality. This article also shows that the DSP control board is stuck on the PCB
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