Industrial Ethernet switch design optimization using FPGA - Database & Sql Blog Articles

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An increasingly popular strategy for non-deterministic communication time for Ethernet protocols is to implement a local clock within each device. Since most devices have microprocessors and (relatively) high-speed clocks, this method is relatively easy to implement. The only limitations of this method are communication latency and system-wide clock synchronization accuracy if accurate clock synchronization can be achieved and maintained throughout the network while controlling the precise timing of the entire system.

This system control method is not suitable for applications such as precise motion control (such as precise control of the motor speed with changing load) because they require a short communication delay between the controller and the device, but it requires highly synchronized system level control. Precise control of the entire system (such as a large printing plant or a long automated production line) is useful. The only constraint on the accuracy of such clock-based control is the system-wide clock synchronization accuracy if there is enough time to send an instruction to each device.

Several industrial network standards (not just Internet-based standards) are using the IEEE 1588 standard to provide this control capability. IEEE1588 provides a highly accurate master clock and a proven clock synchronization mechanism that can be used to generate all local clocks and maintain very accurate system level synchronization with the master clock.

Ethernet-based networks are favored for their low cost and ease of implementation of Ethernet. Ethernet switches are key components that help to take advantage of these, and enterprise systems rely heavily on their high-performance and easy-to-maintain infrastructure. This huge enterprise market for switches means they are easy to implement and cost-effective, but most switches on the market today are not designed for low-latency performance or deterministic routing times, making them difficult to use in industrial environments.

The IEEE1588 system synchronizes the master and slave clocks by detecting host-to-slave communication delays. Placing a switch between the master and slave clocks introduces additional latency because the switch must analyze the packet and then route it. The added delay is not a good thing, but it can be delayed, so it is not the main problem. The biggest problem is that as traffic increases, the time required to route packets increases dramatically.

This is due to the time required to cache, analyze, and route packets to numerous destinations. This change greatly reduces the accuracy of the 1588 clock synchronization, significantly degrading the real-time control performance of the entire system. The measurement of the delay between the 1588 master and slave clocks also depends on the symmetry of the communication time in both directions, because the measurement method used is to count a time-stamped message from the slave clock to the master clock and back from the master clock to the slave clock. The time used is divided by two. In most switch and Ethernet network implementations, this symmetry is unlikely to occur, further reducing the accuracy of clock synchronization.

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Figure 1: Typical Boundary Clock Application Block Diagram

However, the IEEE 1588 standard provides a solution to this problem: if the switch itself has a clock (shown in Figure 1), it can measure the time required for packet routing and integrate it into the synchronous calculation. Since the system does not require this functionality, switches containing such 'boundary' clocks are difficult to see, even if they are generally expensive, and are typically customized for a particular network. With the rapid adoption of IEEE1588-based networks, manufacturers face arduous challenges in how to implement IEEE1588 functionality efficiently and cost-effectively in products and network infrastructure.

It is possible to develop custom ASIC solutions, but as ASIC development costs increase and industrial Ethernet standards change rapidly, developing such solutions is slow, risky, and not cost effective. It is also possible to develop a solution for each protocol using a microprocessor and a third-party ASIC or ASSP for a specific network protocol, but this means implementing a separate solution for each network standard, which is also expensive and inefficient. These solutions may also face problems of lack of flexibility and rapid obsolescence of equipment.

Currently, designers can only avoid these limitations by carefully implementing the network, minimizing the use of switches, or minimizing real-time network traffic. This type of network isolation measures performance levels that are acceptable for some applications, but they are difficult to implement or maintain.

Save development time

Implementing an IEEE1588-enabled switch with an FPGA is an ideal solution to this problem. Altera, National Semiconductor and MorethanIP's respective directors, the three companies jointly provided an optimized eight-port switch design for industrial Ethernet designers, which reduced engineering development time by six to nine months. Development time savings will allow equipment manufacturers to take the lead in time to market.

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Figure 2: Eight-Port Switch Development Board with IEEE1588 Timing Control

Figure 2 shows the development board with embedded IEEE1588 functionality developed by the MorethanIP Enterprise System based on Altera's Stratix II FPGA. The reference design attached to the board enables IEEE1588-enabled switches in a simple, cost-effective manner and is easily modified to accommodate other systems and rapidly changing market demands. These advantages are achieved by the flexibility of the FPGA and a 32-bit RISC processor integrated within the FPGA design.

The Ethernet MAC core and switch fabric kernel intellectual property (IP) with 1588 timing control and programmable uplink functionality was developed by MorethanIPGmbH. The MorethanIP Enterprise System also provides UDP and 1588 software stacks that run on the 32-bit Altera Nios II RISC processor soft core. To provide the best physical interface, the eight-port switch design uses four dual-port PHY transceivers from National Semiconductor's enterprise systems.

The reference design has a clock synchronization capability of less than 100ns and can be used in a variety of applications. This level of accuracy is critical to meeting the demanding communication delays and quality of service (QoS) requirements required for industrial connectivity. Target applications include switches with different industry standards such as Ethernet/IP, ProfiNet, EthernetPowerlink and other Ethernet protocols.

Extend product life cycle

The programmability of the FPGA is the key to the above design advantages. Starting from a single hardware platform, designers can easily implement switches that support different industrial Ethernet protocols (such as EtherCAT, ProfiNet, etc.). The board can support different Industrial Ethernet protocols within the same system or from the same Ethernet port.

This is achieved by implementing different Media Access Controller (MAC) hardware modules and embedded processor software to support different Ethernet standards and IEEE 1588 functionality. The ability to easily reuse previous designs and the availability of off-the-shelf IP means that FPGA-based designs can generate a configuration that supports new features in a very short time compared to designs using ASIC or ASSP devices.

The FPGA loads the hardware configuration and embedded processor software from a serial flash. In the production process, even after the equipment is delivered to the site, it is easy to change the hardware and software functions of the FPGA by rewriting the flash content.

The programmable hardware and software processing power within the FPGA means that designers can integrate the extra features they need through applications that are hardware or software. The ability to implement new features by simply reprogramming the FPGA is a guarantee of the future of the product (eg support for IEEE1588v2.0) and the ability to present new features to customers very quickly.

Because FPGAs have a long life cycle, device manufacturers don't have to worry about potential device end-of-life risks. Because the design is IP-based, it is also convenient to migrate the design to the next-generation FPGA, making it possible for designers to benefit from lower-cost or better performance for next-generation FPGA products. Coupled with the ease of field upgrades, FPGA implementation is the best way to develop products that are easily supported throughout the product lifecycle.

The reference design uses Altera's Stratix II FPGAs, allowing all Nios II processor code to be stored in on-chip memory, but lower cost systems can be implemented using Altera's Cyclone III family of FPGA devices.

Embedded Switch Matrix IP

Figure 3 shows the embedded eight-port switching matrix of the MorethanIPGmbH enterprise system, which contains eight 10/100 Mbps MACs compliant with the Ethernet 802.3 specification, each supporting IEEE1588, which means it can be localized from programmable timers. The synchronous high precision clock "times" each incoming 1588 data frame with a time stamp.

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Figure 3: Block diagram of MorethanIP's eight-port switch architecture in compliance with the IEEE1588 standard

To achieve boundary clock applications, the switch design implements both IEEE1588V1 main and slave applications. The port that communicates with the host is automatically configured as a slave port. The embedded 1588 application generates an accurate clock from the port and forwards the clock information to other ports that are automatically configured as master ports. Tight integration with programmable timers ensures that the clock is synchronized to the master clock within 100ns.

Within the switch, up to two prioritized queues per port can be implemented to provide quality of service (QoS) guarantees for critical services. The switch can also program and prioritize traffic using a 3-bit VLAN priority field, a 6-bit DiffServ Layer 3 code point (IPv4), or an 8-bit service class (IPv6).

The switch design supports IEEE1588 version 1 boundary and version 2 transparent clock applications. The design can be further modified and enhanced to add custom logic, such as adding bridged application software to different system interfaces such as legacy protocols or PCI, to facilitate integration of switches into existing systems.

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Figure 4: IEEE1588 block diagram including software and hardware

In this design, the Nios II embedded processor supports IP configuration and management of the switch, and can run the User Datagram Protocol (UDP) stack, IEEE1588 protocol stack and accurate timing synchronization, and supports dual 10/100 PHY transceiver PHYs. Management and line diagnostics (shown in Figure 4). Embedded processors can also be used for high-level networking functions such as running spanning tree and fast spanning tree algorithms and terminating TCP/IP links. Spanning Tree Protocol (STP) and Rapid Spanning Tree Protocol (RSTP) are link management protocols that support path redundancy and prevent unwanted loops within the network (for industrial Ethernet networks to work properly, only between two nodes) Can have a valid path).

PHY transceiver

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Figure 5: National Semiconductor's PHY Transceiver Block Diagram

Each transceiver has two fully independent 10/100 Mbps ports for multi-port applications, as shown in Figure 5. The transceiver's port switching also allows the two ports to be configured to provide fully integrated range expansion, media conversion, hardware-based fast ns-level fail-over, and port monitoring.

The device integrates multi-port support for common industrial Ethernet topologies. In particular, designers need to have the ability to handle failover under a variety of conditions in order to achieve redundancy support for different applications. Switching from one network stack to another requires no less than a few hundred milliseconds, but some applications, such as security applications, require failover that is extremely fast, preferably at the PHY level. The transceiver within the reference design switches from one port to another at the ns level, even though the host still manages the control path. The architectural improvements in the transceiver's signal path allow performance to far exceed the minimum PHY layer specification requirements and fully address design issues such as jitter and latency. Each Ethernet PHY layer is driven by a reference clock. To minimize jitter, the PHY layer specification requires an extremely accurate clock with an accuracy of less than 50 PPM of the transceiver's 25 MHz reference clock. In addition, in order to meet the specification requirements, the initial jitter must be very small. To solve this problem, a mechanism for tolerating greater jitter is integrated into the architecture. The device architecture also optimizes latency performance for real-time Ethernet operation to ensure minimal switch latency.

In many real-time system implementations, Ethernet packet data transmission delay is an important parameter for normal system operation, and fixed or variable transmission or reception delay in Ethernet PHY will become an important component in system delay calculation. section.

The PHY transceiver is designed to limit the variation in received data latency, which provides a very deterministic system delay. Because the received data is aligned with the receive clock, it avoids the non-deterministic factors that the device typically encounters when receiving data. Therefore, the device can provide highly deterministic receive data delay in MII and RMII modes. In addition, the transceiver can reduce the non-deterministic possibilities that are common in sending RMII delays.

Another important design feature is the built-in cable diagnostics feature that adds forward-looking diagnostics to the traditional time domain reflectometry (TDR) approach used by transceivers. The new fault isolation feature leverages the transceiver's powerful signal processing capabilities to track link quality while data is being transmitted. This highly robust TDR implementation is to send pulses from the receive or transmit conductor pair and observe the results on the two pairs. By observing the type and intensity of the reflected signal on each pair of lines, and by software calculation, the short-circuit and open-circuit conditions of the cable, the distance of the fault point, and which pair are problematic and the pair offset are determined. Proactively monitoring and correcting changes or degraded link quality can reduce system downtime and save on expensive repairs. This feature also detects failures during installation and saves a lot of debugging man-hours.

Summary of this article

Industrial Ethernet technology has been advancing and becoming more popular, and designers are facing an increasingly strong demand for cost-effective industrial switches. ASIC and ASSP-based switches have virtually no new features to customize their system features because of their fixed architecture. In order to increase the feature design, it is generally overwhelming, which leads to additional design time and cost. But the FPGA design that supports IEEE1588 switches as described above saves six to nine months of engineering time and gives designers the coveted flexibility to implement Precision Timing Protocol (PTP), support multiple Industrial Ethernet standards, Additional standard interfaces or other possible custom features.

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