Call chipscope directly in ISE for online logic analysis (2)
The descriptions and calls of each module in chipscope are described in detail in the above references, and will not be described in detail here. Here is just a simple example, to illustrate how I can directly call chipscope Pro Analyzer in ISE for online logic analysis.
First create a project in ISE and enter the following code:
`TImescale 1ns / 1ps
//////////////////////////////////////////////////////////// ////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:26:06 02/26/2010
// Design Name:
// Module Name: mycounter
// Project Name:
// Target Devices:
// Tool versions:
// DescripTIon:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// AddiTIonal Comments:
//
//////////////////////////////////////////////////////////// ////////////////////////////////////
Module mycounter(
Input clk,
// input reset,
Output sout
);
Reg [19:0] cnt=0;
Always @(posedge clk)begin
/* if(!reset)
Cnt<=0;
Else*/
Cnt<=cnt+1;
End
Assign sout=cnt[19];
Endmodule
Here, for the sake of simplicity, signals such as synchronous reset are also masked. I am using a self-made Spartan3 board, where FPGA selects Xilinx's XC3S400-TQC144G; PROM selects Xilinx's XCF02SV0G20C, FPGA's clock pin is P55; and ISE suite uses version 12.2. Then assign the I/O pins in PlanAhead as follows:
# PlanAhead Generated physical constraints
NET "clk" LOC = P55;
//NET "reset" LOC = P11;
NET "sout" LOC = P12;
Next, the code is synthesized, and the core of the Chipscope is created after the error. First click Project---New Source Wizard in the ISE Project Navigator, select the Chipscope DefiniTIon and Connection Wizard, enter the file name, and click Next to produce the .cdc file, as shown in Figure 1.
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