Design Implementation and Simulation Analysis of Rife Algorithm Based on System Generator

Abstract : The Rife algorithm for high-precision frequency estimation is implemented by applying System Generator tool on FPGA platform. Unlike traditional HDL-based and IP-core-based design methods, System Generator tools enable complex algorithms to be implemented faster and more accurately in FPGAs. The description and implementation block diagram of Rife algorithm are given, and the simulation is carried out in System Generator and ISE environment to verify the correctness of the design.

Frequency measurement plays an important role in electronic reconnaissance [1]. With the development of electronic technology, traditional reconnaissance receivers are developing in the direction of digitalization and software [2]. Traditional analog circuit-based frequency measurement methods need to be converted to digital methods. A frequency difference measurement method based on phase difference is usually used in analog reconnaissance receivers [3]. This method can also be conveniently implemented in digital circuits, but the method requires relatively high signal-to-noise ratio [3]. Based on the advantages of digital circuits, advanced algorithms can be used to achieve higher performance. Rife algorithm [4] is a commonly used frequency measurement algorithm based on DFT spectrum, which has the advantages of easy algorithm implementation and high precision. DFT operations can be performed quickly by FFT.

In order to guarantee the probability of interception, the bandwidth of the reconnaissance receiver is constantly increasing, and the instantaneous bandwidth has reached 500 MHz [2]. Traditional DSP and GPP-based systems have been difficult to meet the needs of real-time processing, and FPGA-based signal processors have become a common solution [5-7].

The design method based on HDL and fixed point in FPGA design is different from the traditional C and floating point based design methods in DSP and GPP platforms. The synthesizing of HDL language grammar and language limits the implementation of the algorithm [7-8]. Based on this, Xilinx and Altera have introduced the integrated development tools System Generator for DSP and DSP Builder [9] to simplify the FPGA digital processing system, and quickly and easily convert the abstract algorithm of DSP system into a synthesizable and reliable hardware system. For the DSP designer to clear the obstacles of programming [8-9].

System Generator is a high-performance, efficient DSP algorithm modeling tool that bridges DSP algorithms from FPGAs [7-8]. Its function is shown in Figure 1. The algorithm and system can be modeled in the Matlab/Simulink environment, and the corresponding project is generated. Then ISE is called to simulate, synthesize and realize.

Xilinx provides a large number of signal processing modules (such as FIR filter, FFT), error correction algorithms, memory and digital logic functions for System Generator, which can be directly called in the design environment to quickly build DSP systems. Also supports .m files and HDL import [7-8].

Although only modules provided by Xilinx can be implemented in FPGA in System Generator, the rich resources in Simulink can be used to easily generate test vectors and quickly and accurately analyze the results. Considering the resource consumption, the algorithm implemented in FPGA is dominated by fixed-point algorithm. The accuracy and range of fixed-point algorithm are very limited, and it is easy to overflow or the calculation error is too large, resulting in algorithm failure [5-6]. With traditional HDL-based and IP-based design methods, if the early analysis is incomplete, it is time-consuming and labor-intensive to make changes later in the design, and it is prone to errors. In the System Generator environment, the model-based design method can be used to easily implement and verify the fixed-point algorithm, and it is easy to modify after the problem is discovered.

From the introduction of the Rife algorithm in the first section, the Rife algorithm takes the FFT operation as the core and calculates the frequency value by interpolation of the peak and the sub-peak of the spectrum. The FFT algorithm is a block operation that is performed frame by frame and needs to provide the start and end boundaries of the frame. In this design, the constant false alarm module is used to provide the start and stop signals of the frame. The Rife frequency measurement algorithm implemented in FPGA mainly includes the following functional modules: Fast Fourier Transform Module (FFT), modulo module, peak detection and latching module, Rife calculation module and control module. The overall block diagram of the system is shown in Figure 2.

The FFT module is provided in the System Generator tool. It supports the base 2 and base 4 FFT operations from 8 to 65 536 by parameterized configuration. The implementation in FPGA corresponds to the FFT core in LogicCORE. The use of this module mainly needs to care about the start signal, dv signal and input and output signals. The start signal from the constant false alarm module indicates the start of the conversion by a rising edge. At this time, the data to be converted is input point by point under the synchronization of the clock, and the FFT calculation is started when the number of input signal points reaches the set sampling point. The constant false alarm module will output 0 when no signal is detected, so it will automatically insert 0 when the number of signal points is less than the number of points required by the FFT.

After a period of delay, dv outputs a high level, indicating that the conversion is complete. At this time, the converted spectrum signal is output point by point, and xk_index outputs the index value corresponding to the spectrum point.

The Rife algorithm requires amplitude information of the DFT spectrum, and the FFT module outputs two complex signals of I and Q. The |u|absolute value module performs the absolute value calculation of the spectrum. Implementing such operations in an FPGA requires a large amount of resources. The root number operation can be approximated by the CORDIC module provided by System Generator, which reduces resource consumption. At the same time, the operation of I2+Q2 can be completed by MCode module. MCode implements a finite subset of Matlab functions for rapid development of DSP algorithms and can generate HDL code for FPGA engineering applications.

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