Circuit Design of the Burst Infrared Short-Range Test System
Abstract: Aiming at the characteristics of the torque and speed test of the rotating shaft of the transmission system of the tank armored vehicle, the design idea of ​​the launching circuit of the burst infrared short-range test system of the engine output shaft in a narrow space is proposed.
The use of infrared communication to test the dynamic parameters of the rotating shaft is mainly to meet the strong demand for dynamic parameter testing of moving parts in the narrow space of tanks and armored vehicles. Due to the advantages of infrared communication in space and cost, it has proved its high application value from the above theoretical research and real vehicle test.
The burst infrared short-range test system is a point-to-point infrared data transmission torque test system for narrower spaces such as the engine output shaft based on the infrared short-range test system.
1 Analysis of sampling frequency of tank engine torque signal
The tank engine is a multi-cylinder engine, which works by sequentially firing each cylinder and taking turns to work. The actual measured torque (torque) generated on the engine output shaft is a periodic signal that varies with the speed, and the amplitude of this signal is extremely irregular. The torque in the project is the average torque, which is defined as the average value of the torque in one cycle (720 ° crank angle). High-speed, high-power-density diesel engines are divided into 6-cylinder, 8-cylinder and 12-cylinder, and their maximum speeds do not exceed 3000r / min. From this goal, the 12-cylinder engine with the highest torque signal frequency is used to calculate the torque signal period T.
When nmax = 3000r / min,
T = (10 / nmax) 3.33 (ms)
According to the sampling theorem, the practical sampling frequency is the principle of 5 to 10 times the natural frequency of the signal, and the test of the actual operating effect. The sampling period of the system is 500 μs, that is, the sampling frequency is 2 kHz.
Figure 2 Block diagram of the transmitting part
2 Establishment of a burst infrared short-range test system model
According to Figure 1, a physical model of burst infrared communication is established. The transmitter is installed on the rotating shaft, and the receiver is installed on the rotating shaft. The receiver can be installed in appropriate positions in both axial and radial directions. Because the radial installation is more convenient, it is installed in the radial direction.
Β in Figure 1——receiving half angle of the receiver;
R——the radius of the axis of rotation;
α——the half angle of the transmitter;
L——The minimum distance between receiver and transmitter;
θ——the angle between the transmitter and receiver and the center of the circle;
A-infrared receiving tube; B, C-infrared emitting tube. 
The arc length BC (set to S) is proportional to the communication time, so the size of the arc length S determines the length of the communication time, and the arc length S is called the launch window. The model knows that θ determines the size of the emission window (when R is constant). Only when α is less than or equal to the maximum emission half-angle of the transmitter, the infrared light emitted by the transmitter can be directly received by the receiver. The minimum half-angle of the transmitter currently used is 15 °. When α = 15 °, we can know from the triangle OAB:
(sinβ) / R = sin (π-15 °) / (R + L) (1)
sinβ = R / (R + L) sin15 ° (2)
θ + β = 15 ° (3)
Therefore θ = 15 ° -β
T = 2Rθ / (Rω) = (2θ) / ω (4)
Since θ is proportional to the effective communication arc length AB, and the arc length AB is proportional to the communication time, increasing θ can increase the communication time. From the above formula, there are two ways to increase θ: decrease R, or increase L.
Set the angular velocity of the shaft to ω (rad / s), the number of data sampled in one revolution is N, each data occupies M bits, the baud rate of infrared communication transmission is V (bit / s), it takes time to send N data It is tall (s), and the time for the transmitter to pass through the transmission window (that is, the effective communication time) is T (s), then the total time required to transmit data in one revolution is:
tall = (MN) / V (5)
If the speed is set to 3000r / min, 2θ = 30 °, it can be obtained from (4):
T = 1.67ms
Set N = 200, the sampling frequency
f = 200sps / r & TImes; (3000r / min) / 60 = 10ksps
If M = 16, V = 2Mb / s,
Get:
tall = (200 & TImes; 16) /2M=1.6ms
Thanks to tall 
3 Circuit design of transmitting part
The above analysis of the engine output power signal determines the sampling frequency, and then estimates the minimum storage capacity of the memory, and establishes a data transmission model. To transmit data using the burst side, it is necessary to store all the data collected by one rotation of the shaft, and then send the data to the receiver in the transmission window to realize the instantaneous data. Its characteristic is that there is no need to install a circular receiver. If the radius of the measured axis is large or the measured environment is relatively compact, near-field telemetry is not easy to achieve. However, burst telemetry requires only one or a few receivers.
The structural block diagram of the transmitting part is shown in Figure 2. This part finds the collection of the torque signal and the coding of the digital signal, and puts the collected data in the FIFO memory. When the infrared emission tube receives the digital command, if the acquisition circuit is powered off and enters a low power consumption state, it will notify the power manager to turn on the power supply VCC to allow the acquisition circuit to start working; Take the clock, let the FIFO move out of the data, and send it to the infrared LED to the receiver.
3.1 Data storage
Due to the burst transmission of data, it is necessary to design a memory to store the data collected in one revolution first, and when the transmitter passes through the transmission window, the data is transmitted to the receiver in real time. The memory is one of the key components of the transmitting part, and its selection is directly related to the selection of the A / D converter and the design of the control circuit. The requirement for the memory is that the data collected first is sent first, and then the collected data is sent later, otherwise the receiving part will not be able to restore the original signal correctly, and the purpose of the test cannot be achieved. Therefore, it is necessary to select a 16-bit memory of the first-in first-out FIFO. Since the transmitter is a single channel and can only send data in serial mode, the output of the memory is required to be serial, which can reduce the intermediate link of parallel conversion. If there is a FIFO that goes in and out, then the volume of the transmitting part will be smaller and the control logic is simpler, which is what I hope. But in fact only the parallel in-out serial FIFO and the FIFO with programmable serial-in parallel-serial out four functions are found. Because the latter chip has a large volume and large power consumption, the parallel in-out serial FIFO is selected.
In summary, IDT72105 is selected, with a capacity of 256 & TImes; 16 bits, high speed, low power consumption, and synchronous / asynchronous FIFO memory with independent receiving and sending clock control. It not only provides storage space as a data buffer, but also acts as a flexible memory between the EPP parallel bus and the A / D converter, so there is no need to consider synchronization and coordination between each other. The advantage of FIFO is that the read and write timing requirements are simple, and there is a ring pointer for reading and writing inside, and no additional address information is required when operating the chip. When it receives the access instruction SOCP issued by the infrared emission tube, the synchronization frame signal is input to the TXD end of the infrared emission tube through the SO terminal and transmitted.
Figure 5 Monitoring code encoder and frame structure
3.2 Data acquisition circuit
Because the FIFO of parallel input and serial output is selected, it is best to select the A / D converter with parallel output and require a single power supply. Therefore, the AD7472 of AD company is selected with a resolution of 12 bits, low power consumption, and a power supply range of 2.7 ～ 5.25V. AD7472 converter can work in three modes: (1) High Sampling mode (High Sampling); (2) Sleep mode (Sleep Mode); (3) Burst mode (Burst mode). Because the sampling frequency of the system is not high (4kHz), the burst mode of the AD7472 is used, which is the same as the second mode, except that the input clock (CLK IN) is not continuous, and the clock signal is only provided during the conversion, which can reduce power consumption .
In this mode, when the rising edge of CONVST comes, it takes 1μs for the converter to enter the wake-up period (tWAKEUP). During this period, if the falling edge of CONVST has come, the A / D does not immediately enter the conversion period until after 1μs; If the falling edge arrives after 1 μs, the converter starts conversion at the moment of the falling edge, and the entire conversion takes 14 clock cycles. It is worth noting that when the BUSY signal is high, the clock signal should appear within two clock cycles, and the state of the data bus cannot be changed during the conversion. The actual design sampling frequency and the timing of the reading control circuit are shown in Figure 3. The frequency of the CONVST signal is the sampling frequency of 4kHz, the period is 250μs, and the forward pulse width is 2μs. That is, after the A / D wakes up, the data conversion starts again after 1μs. The RD signal uses this 1μs to read the A / D.
3.3 Synchronous frame circuit design
Because the system records the data collected in one revolution in the FIFO memory and the data transmission method is wireless serial communication, it is necessary to open the data in the form of frames to facilitate the decoding of the receiving part. The author designed a 16-bit synchronization code. The highest bit is low, which is used to partition frame and frame data. The lowest bit is also set to low, which is used to separate the synchronization frame and data, and to provide shift pulse generation time for decoding. In addition to the synchronization code, a frame of data consists of 8 16-bit sample data, a total of 112 bits. The circuit that generates the step code is shown in Figure 4.
Figure 6 Take the data control circuit
3.4 Monitoring code encoder and frame structure
The FIFO memory word length is 16 bits, the A / D converter is 12 bits, and 4 bits remain. In order to enhance the credibility of the data and the error correction capability of the data, four monitoring codes are designed, distributed on both sides of the data, as shown in Figure 5. The four monitoring codes are locked in the element 74L5243, and each write signal comes when Need to write 4-digit monitoring code. Since these 4 monitoring codes are distributed on both sides of the 12-bit data, after receiving the data at the receiving end, these 4 monitoring codes are detected first; if the monitoring codes are correct, the received data is credible; if there are errors, there are It may be moved forward or backward by one. If after these corrections, the 4-bit monitoring code matches the actual situation, the data can be corrected. If they do not match, the data is unspeakable.
3.5 Access control circuit
Due to the burst mode for data transmission, only when the transmitting tube enters the communication window and the transmitting tube and the receiving tube establish a data link can they enter the data transmission. The infrared transmitting tube can receive the fetching instruction and send it to the counter for counting. If the counter is full, it means that the fetching instruction has arrived and the transmitting tube is passing through the communication window, then the transmission link is established. 4013 is triggered, the access clock SOCP is turned on, and all the data in the FIFO is transmitted to the receiver. The fetch control circuit is shown in Figure 6.
The circuit design of the above transmitting part has been proved by simulation experiments to achieve the design purpose of bursting the signal.
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