Microelectronics, integrated circuits
University of Science and Technology) // Optical Technology. One 2001, 27 (4). ―348-349,351 carried out error analysis on the mathematical model of dual CCD intersection coordinate measurement, and proposed the conditions for optimal structural parameters. Through the method of computer simulation, the structural parameters measured by the intersection of the two CCDs were optimized, and the optimization results for different target surface sizes were obtained. It theoretically proves the conclusion of "the orthogonal intersection of optical axes" when the two CCDs intersect the coordinate measuring disk. Table 1 Reference 9 (wood) low voltage Class C SiGe microwave power heterojunction bipolar transistor / Jia Hongpei, Chen Peiyi, Qian Peixin, Pan Hongshu, Huang Jie, Yang Zengmin, Li Mingyue (Tsinghua University Institute of Microelectronics) // Semiconductor The device structure and test results of low voltage microwave SiGe power heterojunction bipolar transistor (HBT) are given. The device structure is suitable for low voltage and high current applications. It adopts the horizontal layout design of comb-shaped emitter strip, and its working voltage is 3 * 4V. In the working state of C type, the output power can reach 1.65W under the working frequency of 1GHz, and the highest can be achieved when the gain is 8dB * 3V The collection efficiency is 67.8%, ref. 5 (wood) 8, microelectronics, integrated circuit nanoelectronics research and prospects / Wen Dianzhong, Li Guodong, Zhao Xiaofeng (Heilongjiang University) Journal of Natural Science of Heilongjiang University. One 2001, 18 (3). ―59-64 On the basis of expounding the concept, meaning and connotation of nanoscience and technology, we focused on the main fields and development prospects of nanoelectronics research and development in the 21st century. Table 1 Refer to 44 (Wood) Hierarchical Segmented P / G Network Equivalent Resistance Solving Algorithm for Memory Chips / Zhu Hongwei, Yan Xiaolang, Sun Lingling, Ma Qi (Department of Information and Electricity, Zhejiang University) // Journal of Circuits and Systems The size of the / G network is huge, which is a problem for calculating the equivalent resistance between nodes in the resistance network. Directly using conventional linear equations to solve algorithms can not meet the constraints of memory space and running time. Aiming at the characteristics of the imbalanced association density of the layout network, a hierarchical network segmentation algorithm is proposed in this paper, which divides the global network into solvable subnets by layers, and uses the equivalent subnet algorithm to achieve fast calculation of multiple observation points. Table 1 Reference 6 (gold) improved high-level power consumption estimation methods / Yang Jun, Long Xing, Hu Chen, Shi Youhua (National Engineering Research Center for Integrated Circuit System of Southeast University) Journal of Circuits and Systems. One 2001, 6 (4). * 38- The article discusses the high-level power consumption estimation method of integrated circuits, and proposes a more accurate power consumption estimation method for the linear bit correlation coefficient model, which can be used for power-driven VLSI high-level synthesis. The experimental results show that when the signal is a stationary time series with limited parameters, this estimation method has higher accuracy than the original method of replacing strong correlation bit correlation coefficients with signal correlation coefficients, thereby improving the module design in VLSI high-level design. Accuracy of power consumption estimation. Table 3 Reference 5 (Gold) Hierarchical Time Driven Layout Design Based on 25 / xm Process / Han Xiaoxia, Zhang Ming, Wu Wanli, Yao Qingdong (Zhejiang University) 丨 丨 Journal of Circuits and Systems. An integrated circuit (1C) has evolved into the era of system on chip (SOC). The ultra-deep submicron system chip has a large scale. Due to the characteristics of high complexity and fast system clock frequency, the traditional design process has been difficult to apply to the design of system chips due to the limited design scale and the difficulty of timing closure. The RISC core design of the fixed-point pipeline / Wei Jian, Zhang Ming, Zhou Qiongfang, Yu Yan, Yao Qingdong (Zhejiang University) "Journal of Circuits and Systems. One 2001, 6 (4).
From the perspective of developing instruction-level parallelism ILP, the paper analyzes the architecture characteristics of the super-standard and super-pipeline processor, and gives a fixed-point RISC core design on this basis. The design uses a Top-down design method, including three pipeline execution units, dynamic scheduling of instructions, and a non-blocking cache non-blocking-caches mechanism. Reference 3 (gold) SSN research and its application in the VLSI design process / Xu Donglin, Guo Xinwei, Xu Zhiwei, Lin Yue, Ren Junyan (Electronic Journal of the State Key Laboratory of Special Integrated Circuits and Systems for Fudan University. 1 2001, 29 (11) ―1471-1474 details one of the main reasons for the synchronous switching noise (SSN) affecting the popularity of VLSI circuits; the parasitic inductance of the chip-package interface. According to the insertion of power / ground pins in the chip, the chip is reduced -The idea of ​​the parasitic inductance of the package interface, a simple and effective method for optimizing the layout of the output driver based on SSN performance is proposed and integrated into the VLSI design flow. It is verified with a 0.6 micron CMOS process. The results show that the optimized design can Effectively reduce the impact of SSN on the reliability of VLSI circuits Table 2 Ref. 6 (Gold) A fast three-dimensional VLSI interconnect capacitance extraction method: virtual multi-media method / Yu Wenjian, Wang Zeyi, Hou Jinsong (Department of Computer Science and Technology, Tsinghua University) "Journal of Electronics.
In this paper, a virtual multi-media (Quasi-MultipleMedium, QMM) acceleration method based on direct boundary element method is proposed and applied to the calculation of three-dimensional VLSI multi-media interconnect capacitance. The QMM method treats a single-layer dielectric in a three-dimensional interconnect capacitor as being composed of multiple virtual media, thereby greatly reducing the number of non-zero elements in the coefficient matrix, and ultimately significantly reducing the calculation time and storage space. By comparing the QMM algorithm with the non-QMM algorithm, and the commercial software Raphael's calculation of the actual three-dimensional interconnection structure, the results show that the QMM calculation can maintain the accuracy of the calculation while improving the efficiency of capacitor extraction. Table 3: Two-dimensional analysis of the surface field distribution of the 12 (gold) plane junction plate structure / He Jin, Zhang Xing, Huang Ru, Wang Yangyuan (Institute of Microelectronics of Peking University)》 Journal of Semiconductors. One 2001, 22 (7). 915-918 proposed a two-dimensional surface electric field analytical physical model of planar junction field plate structure based on the solution of two-dimensional Poisson equation. Based on the model, the effects of substrate doping concentration, field plate thickness and length on the two-dimensional surface field distribution were analyzed. The predicted field distribution and breakdown voltage calculation results are basically consistent with the previous numerical analysis. This model provides a theoretical basis for the optimal design of the field plate structure.
Refer to the dynamic characteristics of the micro-microphone with 11 (wood) grain structure: Top-down design using EDA / GAD tools A silicon S micro microphone was systematically simulated. The optimized values ​​of various parameters were obtained, and the optimized micro microphone had a flat response in the audio range. On this basis, a top-down optimization was proposed The design method accurately predicts the behavior of the system, and analyzes the interaction of various components and their impact on the performance of the system. Table 2 refers to the development and prospect of 9 (wood) RF microelectromechanical system / Yuan Mingwen (Hebei Semiconductor Institute) "Semiconductor Introduced the latest developments, research contents and top applications of radio frequency microelectromechanical systems (RFMEMS). The system devices include switches, relays, capacitors, inductors, filters and microwave and meter-wave components. 2 ref. 22 (noon) Status and development of SOC / Wu Hongjiang, Zheng Bin (13 Institute of Electronics) "Semiconductor Information.
Introduced the progress of SOC, MEMS, MCM, made a brief description of SOC design and IP core development, and proposed the work that China should carry out in the field of SOC. (Noon) 320x240 infrared focal plane array drive circuit miniaturization design research / Li Yingwen, Yi Xinjian, He Zhaoxiang, Luo Yan (Huazhong University of Science and Technology) 丨 / Infrared and laser engineering. In this paper, the 320x240 infrared uncooled focal plane drive circuit and the digital design method of the focal plane array analog output signal are proposed. Adopt Xilinx's XC9500 series of integrated programmable logic devices to design sequential circuits to achieve circuit miniaturization. Designed with VHDL language, it is easy to modify the logic of the circuit during the trial production process. The 5.5M analog signal output from the focus plane of TI's A / D converter THS1408 is used for analog-to-digital conversion, which reduces the interference in the subsequent transmission process. It laid the foundation for the development of 320x240 staring uncooled infrared thermal imager. Reference 2 (wood) silicon substrate microwave integrated circuit / Mao Junfa (Shanghai Jiaotong University) 丨 Microwave Journal. In 2001, silicon substrate microwave integrated circuits had attractive development prospects. The article expounds the advantages of using silicon materials as substrates for microwave integrated circuits, analyzes the electrical performance of silicon substrate microwave transmission lines, passive components and germanium silicon heterojunction bipolar transistors (SiGeHBT) The progress of microwave integrated circuit research, and the characteristics and applications of digital circuit and RF and microwave circuit mixed integration on silicon substrate were discussed. Table 1 Reference 30 (Xu) LSC87 embedded coprocessor implementation method of transcendental functions / Liang Zheng, Yang Yintang, Shen Xubang (Xi'an Institute of Microelectronics) "Journal of Xidian University One 2001, 28 (2). -Introduced the commonly used transcendental function implementation method in the math coprocessor, analyzed the advantages and disadvantages of the transcendental function implementation algorithm in the intelsos coprocessor, and discussed the transcendental function implementation method of the embedded coprocessor LSC87. In order to optimize the design scale and speed, the trigonometric function directly uses the transcendental function to implement the algorithm, and the exponential function and the logarithmic function use the RESTORINGSHIFT-AND-ADD algorithm. Under the premise of basically maintaining the original coprocessor data path structure, the speed of function calculation has been greatly improved. Table 2 Reference 2 (Gold) VLSI yield optimization design method based on subunit level redundancy / Zhao Tianxu, Ma Peijun, Hao Yue, Jiao Yongchang (Xidian University of Microelectronics) J Journal of Xidian University. -2001, 28 (3). -283-286 describes the optimal allocation model of subunit-level redundancy using the optimization idea, and gives a global optimal solution using genetic algorithm. This model considers two factors that affect the yield: the average density of defects D and the ratio of the area of ​​the supporting circuit to the total area of ​​the unit. All the iso-Q lines must be recalculated, and the efficiency is very low. However, the optimization technique proposed here does not calculate all the inductance layout design schemes when calculating, so the calculation efficiency is greatly improved. Comparing the calculation results with the measured fi parameters of the corresponding design scheme, there is only about 5% calculation error. The calculation results are compared with the best design scheme of the iso-Q line under the same conditions. This optimization technique can always get the best scheme that is basically consistent with it. In fact, due to the flexibility of this optimization technique, the "real" best design plan can only be derived from this optimization technique, and the iso-Q line can only get the "relative" best design plan, table * 2.5Gb / sGaAsMESFET timing decision circuit / Zhan Yan, Xia Guanqun, Wang Yongsheng, Zhao Jianlong, Zhu Chaosong (Shanghai Institute of Metallurgy, Chinese Academy of Sciences) // Journal of Semiconductors. 1. Designed a timing decision circuit for the exhausted GaAsMESFET of 2.5Gb / s optical fiber communication. The SPICE simulation shows that the recovered clock frequency reaches 2.5 Hz, and the transmission rate of the decision circuit reaches 2.5 Gb / s. Experiments prove that the decision circuit can generate the correct digital signal after sampling the clock signal, and the transmission rate reaches 2.5 Gb / s * Ref. 8 (Wood ) Linear horizontal analog integrated circuit fault testing and diagnosis: short-circuit admittance parameter method / Li Feng, Shang Yunliang, Kong Qingsheng (Fudan University), Journal of Applied Sciences. 1 2001, 19 (3).
* 228-232 proposes a method for testing and diagnosing faults in linear analog integrated circuits: short-circuit admittance parameter method. This method can determine whether the circuit is normal or faulty by performing two voltage tests on the external port of the circuit; the ihai method can be used to design an automatic circuit test device, which is applied to the automatic test or maintenance of the linear analog integrated circuit production line The personnel determine whether the linear analog integrated circuit in the electronic device is faulty. Its outstanding advantage is the ability to suppress component parameter tolerance and test and calculation errors. Table 1 Reference 8 (Wood) A 128x128 CMOS Snapshot Mode Focal Plane Readout Circuit Design / Chen Zhongjian, Li Xiaoyong, Yu Songlin, Han Jianzhong, Ji Lijiu (Peking University Microelectronics Lang // Journal of Electronics. An article on a working in snapshot mode The new structure of the CMOS focal plane readout circuit. A cable circuit uses only 4 MOS tubes. It uses a special layout design and uses a PMOS tube as a reset tube. This not only ensures that the storage capacitor in the pixel is large enough, but also avoids the threshold loss of the reset voltage. Improve the charge processing capability of the readout circuit. Because the pixel circuit is very simple, and the structure can effectively eliminate the influence of the parasitic capacitance of the column line C6us, so the structure is very suitable for small pixels, large-scale focal plane readout circuit. Using DCA The structure and the 1.201 double double stroke (DPDM-Double-PolyDouble-Metal) standard CMOS process design a 128x128 scale focal plane readout circuit test chip with a pixel size of 50x50 / im2 and a charge processing capacity of 11.2pC. This is described in detail in the article. The architecture of the readout circuit, pixel circuit, detector model and working timing, and gives accurate HSPICE simulation results Test chip test results. Table 1 refers to the 8 (gold) Boole method in the VLSI layout / Liu Yanpei (Northern Jiaotong University) // China Science Series A * 2001, 31 (10). * 871-877 uses the Boole method to discuss those The embedding of graphs related to VLSI layout is mainly in the general theory of graph flatness, orientability, and vertical and horizontal layout, etc. It seems to have similarities and similarities. See 13 (wood) for an improved VLSI key area calculation model and method / Ma Peijun, Hao Yue, Kou Yun (Xidian University of Electronic Science and Technology) 丨 丨 Journal of Semiconductors. 1 2001, 22 (9). * 1212-1216 studied the existing key area calculation model from the fault mechanism and improved its open circuit / Calculate the fault core of the short-circuit key area calculation model to obtain a key area calculation method suitable for general layout graphic structures. This is of great significance for calculating the VLSI key area, guiding layout optimization design, and improving 1C yield. See 9 (Wood) CPU Bridge Design of CPU Simulator in ASIC Design / Deng Rang Xing Zuocheng, Xie Lunguo (School of Computer Science and Technology, National University of Defense Technology) // Computer Engineering and Applications. A functional simulation is to design high-performance microprocessing The IE interface of the interface ASIC chip is to eliminate the functional design error of the ASIC. In order to better simulate the ASIC chip, the CPU model must be flexible, convenient, and can reflect the behavior of the microprocessor. The article will introduce the The development of a CPU behavior simulator is described in Part 2 (Just) Implementation of DVB Stream Synthesis and Transmission System Based on PCI Bus / Zhang Dengfu, Jiang Dazong, Bi Duyan, Mao Baixin (Xi'an Jiaotong University Biomedical Engineering Institute) // Computer Engineering and Application -2001, 37 (1). -101-103 This article discusses the use of S5920 and PLD to realize the data transmission between TMS320C32 and PCI bus, and the specific scheme of co-processor to complete the DVD stream synthesis; combined design gives MAX + PLUSn Use and operation timing of FIFO module in software. Aiming at the formation of DVB transmission stream, the use of synchronous triggering and twice the input clock to eliminate glitches in the design of complex sequential logic is discussed. The results show that this method is very effective.
Reference 5 (gang) 9. Application of electronic components and components electrorheological fluid in semi-active control of wind vibration of feed support system of large radio telescope / Su Yuxin, Duan Baoyan, Nan Rendong, Peng Bo (Xidian University of Electronic Technology) // Xi'an University of Electronic Science and Technology m. Aiming at the problem of random wind-induced vibration response of the suspension feeder support system of the large radio telescope, on the basis of simply introducing the forms of electrorheological fluid and electrorheological damper, an electrorheological adjustable damping is designed To realize the semi-active control of wind vibration of large cable telescope suspension feed support system. The mechanical model of the rheological adjustable damper was deduced in detail, and the effectiveness of the designed adjustable damper was verified by computer simulation. Completely solved the problem of additional damping control of the suspension drag system. Figure Digital Potentiometer DS1867 Application in Grain Drying Tower Moisture Measurement and Control System / Yang Yuxiang, Wang Kening, Teng Zhaosheng (Hunan University) 丨 丨 Instrument Technology. One 2001, (4).
* 17-19 By analyzing the working principle of the digital potentiometer DS1867, the method used as a D / A converter in the moisture measurement and control system of the grain drying tower is introduced, and the hardware circuit and software flow are provided for the D / A converter The design and application of digital potentiometer provide a new idea. Reference terminal characteristics and application of lossless resistors / Wu Jianhua, Yin Hongyi, Xu Xinhe (Northeastern University) W Journal of Northeastern University. One 2001, 22â‘·. Yi 370 ~ 372 analyzed and discussed the characteristics and functions of lossless resistors, established the mathematical model and application method of lossless resistors, and replaced the resistors in the circuit with lossless resistors, realizing the dynamic circuit The characteristic correction greatly reduces the energy disk loss of the circuit. The experimental results verify the correctness of the characteristic analysis and algorithm, indicating that the lossless resistor can be used in various electrical systems and automatic control systems. Reference 8 (Wood) New Energy Device I ~ Latest Developments in Research and Development of Primary Capacitors / Zhong Haiyun, Li Jian, Su Yanyang, Li Qingkui (School of Information Science and Engineering, Central South University) // Power Technology introduces the working principle and structural characteristics of supercapacitors, And summarized the latest domestic and foreign research development trends and industrialization. Supercapacitors are a new type of energy devices that have appeared in recent years. They have the advantages of conventional capacitors with high power density and rechargeable battery solidity: high density, fast charging and discharging, and long life. It is hopeful that they will develop into a new type, high efficiency, and practical. The fl can store equipment. The working principle and structural characteristics of supercapacitors are very different from ordinary capacitors. Supercapacitors are mainly composed of polarized electrodes. Collector, electrolyte, separator. The lead and the packaging material are composed of several parts, and the composition and structure of each part have a significant impact on its performance. Table 1 Ref. 23 (Wood) / Properties of YBC0 / Pt / Ti02 / Si02 / Si / Li Qiliang, Wang Xusheng, Yin Jiang, Xingsen Sen, Liu Zhiguo (Nanjing University), Journal of Nanjing University (Natural Science).
Recent studies have shown that the use of conductive oxides as electrodes can partially improve the fatigue and
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